The invention lies in the memory technology field and relates, more specifically, to a memory system having data lines for transmitting data between memory components and at least one control unit.
Prior art memory systems have an interface unit which contains a central control unit and data lines. The data lines are to be found with control lines in a bus system which connects memory components in quasi-parallel.
The prior art memory systems have the disadvantage that the access time increases as the size of the memory increases.
The object of the present invention is to provide a memory system which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which further shortens the access time to data held in the memory components to a minimum.
With the above and other objects in view there is provided, in accordance with the invention, a memory system, comprising:
a plurality of memory components;
a central control unit;
a group control unit having a plurality of data lines for transmitting data between the memory components and the central control unit;
the data lines including a first data line connected to the central control unit, and second data lines connected to a group of the memory components.
In other words, the invention achieves the above objects by virtue of the fact that a memory system of the generic type is configured such that it has at least one central control unit and at least one group control unit, the group control unit having at least one first data line for connecting the group control unit to the central control unit, and second data lines for connecting a group of memory components to the group control unit.
The invention thus aims to provide a memory system which permits hierarchically organized access to data in individual memory components or memory chips.
In accordance with an added feature of the invention, at least one subgroup control unit is connected to the second data lines and third data lines connected between the subgroup control unit and the memory components, whereby the memory components are connected to the central control unit via the first data line, the group control unit, the second data lines, the subgroup control unit, and the third data lines.
In accordance with an additional feature of the invention, the third data lines are electrically isolated from one another by the subgroup control unit. Preferably, the third data lines radiate in a star pattern from the subgroup control unit.
Similarly, in accordance with another feature of the invention, the second data lines are electrically isolated from one another by the group control unit. Preferably, the second data lines radiate in a star pattern from the group control unit.
In accordance with a further feature of the invention, a plurality of first data lines are electrically isolated from one another by the group control unit. In the preferred embodiment, the first data lines radiate in a star pattern from the group control unit.
In accordance with again another feature of the invention, the group control unit and/or the subgroup control unit and/or the central control unit contains a full buffer chip or is formed by a full buffer chip.
One of the subjects of the invention is thus an embodiment of a new organization form for the memory components. In this context, memory components are split into m groups of memory components. Suitable components, in particular amplifiers, such as buffers or repeaters, are used to electrically isolate the memory components from one another.
The central control unit is connected to M=m*x data lines, where x denotes the number of data lines to the individual memory components. The data path between the central control unit and a processor unit, such as a CPU (Central Processor Unit), likewise has M=m*x data lines.
Expediently, an even greater number of memory components are driven by the central control unit by virtue of the fact that the second data lines are connected to at least one subgroup control unit, and that the memory components are connected via the central control unit, the first data line, the group control unit, the second data lines, the subgroup control unit, and via third data lines, the third data lines connecting the memory components to the subgroup control unit.
The object of this particularly advantageous embodiment of the memory system is thus to provide at least three hierarchical levels of connections for the memory components.
This provides a memory system for a large number of memory components.
In principle, implementation of the invention requires only that at least one group control unit be present in addition to the central control unit. However, the efficiency of the memory system is increased by a greater number of group control units.
Further control units, which are provided in addition to the particularly expedient subgroup control units and connect additional hierarchical levels, make it possible to connect several hundred memory components. Such a greater number of hierarchical levels and various control units is expedient, above all, when there is a particularly large number of memory components. Particularly fast access times can be produced by virtue of the fact that the data lines are DC-isolated from one another, and the control unit to which they are connected connects them electrically only in selected switching states.
In the case of the particularly advantageous memory system having at least one subgroup control unit, it is therefore expedient that the third data lines are electrically isolated from one another by the subgroup control unit. A particularly preferred embodiment of the memory system is distinguished by the fact that the third data lines leave the subgroup control unit in a star form.
It is likewise expedient that the second data lines are electrically isolated from one another by the group control unit.
A likewise preferred embodiment of the memory system is distinguished by the fact that the second data lines leave the group control unit in a star form.
It is particularly expedient that the memory system has a plurality of first data lines, and that the first data lines are electrically isolated from one another by the group control unit.
A further preferred embodiment of the memory system is distinguished by the fact that the first data lines leave the group control unit in a star form.
It is particularly expedient that the data lines are used to implement bidirectional data interchange between the central control unit and the individual memory components in two-point networks. In this context, two-point lines having bidirectional driver and receiver circuits are involved. The choice of internal resistance for the respectively active one of the two bidirectional driver and receiver circuits in the two-point line allows the line system to be closed so that it is always active, using its characteristic impedance. Thus, signals which are reflected from an open (that is to say, remote from an active driver) end of the line and return to the driver are absorbed. This is true for the drivers on both sides of the bidirectional network, the driver opposite the active driver being in a high-impedance state.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory system, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of the specific embodiment when read in connection with the accompanying drawing.